[PATCH 00/10] MIPS: lantiq: various fixes

[John Crispin]

This is the firt lot of patches that have been staged inside openwrt for a
while. There are also fixes for pinctrl, serial and gpio coming up and 2 new
drivers for nand and i2c on falcon.

John Crispin (10):
MIPS: lantiq: handle vmmc memory reservation
MIPS: lantiq: add reset-controller api support
MIPS: lantiq: reboot gphy on restart
MIPS: lantiq: add support for xrx200 firmware depending on soc type
MIPS: lantiq: export soc type
MIPS: lantiq: move eiu init after irq_domain register
MIPS: lantiq: copy the commandline from the devicetree
MIPS: lantiq: the detection of the gpe clock is broken
MIPS: lantiq: add missing spi clock on falcon SoC
MIPS: lantiq: refactor the falcon sysctrl code

arch/mips/Kconfig | 2 +
arch/mips/include/asm/mach-lantiq/lantiq.h | 2 +
arch/mips/lantiq/falcon/sysctrl.c | 108 ++++++++++++----------------
arch/mips/lantiq/irq.c | 48 ++++++-------
arch/mips/lantiq/prom.c | 7 ++
arch/mips/lantiq/xway/Makefile | 2 +
arch/mips/lantiq/xway/reset.c | 70 +++++++++++++++++-
arch/mips/lantiq/xway/vmmc.c | 69 ++++++++++++++++++
arch/mips/lantiq/xway/xrx200_phy_fw.c | 23 +++++-
9 files changed, 244 insertions(+), 87 deletions(-)
create mode 100644 arch/mips/lantiq/xway/vmmc.c

[John Crispin]

The Lantiq SoCs have a 2nd mips core called "voice mips macro core (vmmc)"
which is used to run the voice firmware. This driver allows us to register
a chunk of memory that the voice driver can later use for the 2nd core.

Signed-off-by: John Crispin <***@openwrt.org>
---
arch/mips/lantiq/xway/Makefile | 2 ++
arch/mips/lantiq/xway/vmmc.c | 69 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 71 insertions(+)
create mode 100644 arch/mips/lantiq/xway/vmmc.c

diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 087497d..a2edc53 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,3 +1,5 @@
obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o

+obj-y += vmmc.o
+
obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
diff --git a/arch/mips/lantiq/xway/vmmc.c b/arch/mips/lantiq/xway/vmmc.c
new file mode 100644
index 0000000..696cd57
--- /dev/null
+++ b/arch/mips/lantiq/xway/vmmc.c
@@ -0,0 +1,69 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Copyright (C) 2012 John Crispin <***@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
+#include <linux/dma-mapping.h>
+
+#include <lantiq_soc.h>
+
+static unsigned int *cp1_base;
+
+unsigned int *ltq_get_cp1_base(void)
+{
+ if (!cp1_base)
+ panic("no cp1 base was set\n");
+
+ return cp1_base;
+}
+EXPORT_SYMBOL(ltq_get_cp1_base);
+
+static int vmmc_probe(struct platform_device *pdev)
+{
+#define CP1_SIZE (1 << 20)
+ int gpio_count;
+ dma_addr_t dma;
+
+ cp1_base =
+ (void *) CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE,
+ &dma, GFP_ATOMIC));
+
+ gpio_count = of_gpio_count(pdev->dev.of_node);
+ while (gpio_count > 0) {
+ enum of_gpio_flags flags;
+ int gpio = of_get_gpio_flags(pdev->dev.of_node,
+ --gpio_count, &flags);
+ if (gpio_request(gpio, "vmmc-relay"))
+ continue;
+ dev_info(&pdev->dev, "requested GPIO %d\n", gpio);
+ gpio_direction_output(gpio,
+ (flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
+ }
+
+ dev_info(&pdev->dev, "reserved %dMB at 0x%p", CP1_SIZE >> 20, cp1_base);
+
+ return 0;
+}
+
+static const struct of_device_id vmmc_match[] = {
+ { .compatible = "lantiq,vmmc-xway" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, vmmc_match);
+
+static struct platform_driver vmmc_driver = {
+ .probe = vmmc_probe,
+ .driver = {
+ .name = "lantiq,vmmc",
+ .owner = THIS_MODULE,
+ .of_match_table = vmmc_match,
+ },
+};
+
+module_platform_driver(vmmc_driver);

[John Crispin]

Add a reset-controller binding for the reset registers found on the lantiq
SoC.

Signed-off-by: John Crispin <***@openwrt.org>
---
arch/mips/Kconfig | 2 ++
arch/mips/lantiq/xway/reset.c | 61 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 380cce3..46bee77 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -268,6 +268,8 @@ config LANTIQ
select USE_OF
select PINCTRL
select PINCTRL_LANTIQ
+ select ARCH_HAS_RESET_CONTROLLER
+ select RESET_CONTROLLER

config LASAT
bool "LASAT Networks platforms"
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 1fa0f17..a1e06b7 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -14,6 +14,7 @@
#include <linux/delay.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
+#include <linux/reset-controller.h>

#include <asm/reboot.h>

@@ -113,6 +114,66 @@ void ltq_reset_once(unsigned int module, ulong u)
ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
}

+static int ltq_assert_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ u32 val;
+
+ if (id < 8)
+ return -1;
+
+ val = ltq_rcu_r32(RCU_RST_REQ);
+ val |= BIT(id);
+ ltq_rcu_w32(val, RCU_RST_REQ);
+
+ return 0;
+}
+
+static int ltq_deassert_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ u32 val;
+
+ if (id < 8)
+ return -1;
+
+ val = ltq_rcu_r32(RCU_RST_REQ);
+ val &= ~BIT(id);
+ ltq_rcu_w32(val, RCU_RST_REQ);
+
+ return 0;
+}
+
+static int ltq_reset_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ ltq_assert_device(rcdev, id);
+ return ltq_deassert_device(rcdev, id);
+}
+
+static struct reset_control_ops reset_ops = {
+ .reset = ltq_reset_device,
+ .assert = ltq_assert_device,
+ .deassert = ltq_deassert_device,
+};
+
+static struct reset_controller_dev reset_dev = {
+ .ops = &reset_ops,
+ .owner = THIS_MODULE,
+ .nr_resets = 32,
+ .of_reset_n_cells = 1,
+};
+
+void ltq_rst_init(void)
+{
+ reset_dev.of_node = of_find_compatible_node(NULL, NULL,
+ "lantiq,xway-reset");
+ if (!reset_dev.of_node)
+ pr_err("Failed to find reset controller node");
+ else
+ reset_controller_register(&reset_dev);
+}
+
static void ltq_machine_restart(char *command)
{
local_irq_disable();

[John Crispin]

A reboot sometimes lead to a none working phy. An explicit reboot fixes the
problem.

Signed-off-by: John Crispin <***@openwrt.org>
---
arch/mips/lantiq/xway/reset.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index a1e06b7..fe68f9a 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -176,8 +176,15 @@ void ltq_rst_init(void)

static void ltq_machine_restart(char *command)
{
+ u32 val = ltq_rcu_r32(RCU_RST_REQ);
+
+ if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
+ val |= RCU_RD_GPHY1_XRX200 | RCU_RD_GPHY0_XRX200;
+
+ val |= RCU_RD_SRST;
+
local_irq_disable();
- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | RCU_RD_SRST, RCU_RST_REQ);
+ ltq_rcu_w32(val, RCU_RST_REQ);
unreachable();
}

[John Crispin]

VR9 needs different firmware files for the various phy/soc revisions. S=
ome
boards are ship with older and newer SoC revisions. To be able to boot =
a single
image on all versions we need to define both firmware files inside the
devicetree.

Signed-off-by: =C3=81lvaro Fern=C3=A1ndez Rojas <***@gmail.com>
Signed-off-by: John Crispin <***@openwrt.org>
---
arch/mips/lantiq/xway/xrx200_phy_fw.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/mips/lantiq/xway/xrx200_phy_fw.c b/arch/mips/lantiq/x=
way/xrx200_phy_fw.c
index d4d9d31..7c1e54c 100644
--- a/arch/mips/lantiq/xway/xrx200_phy_fw.c
+++ b/arch/mips/lantiq/xway/xrx200_phy_fw.c
@@ -24,7 +24,28 @@ static dma_addr_t xway_gphy_load(struct platform_dev=
ice *pdev)
void *fw_addr;
size_t size;
=20
- if (of_property_read_string(pdev->dev.of_node, "firmware", &fw_name))=
{
+ if (of_get_property(pdev->dev.of_node, "firmware1", NULL) ||
+ of_get_property(pdev->dev.of_node, "firmware2", NULL)) {
+ switch (ltq_soc_type()) {
+ case SOC_TYPE_VR9:
+ if (of_property_read_string(pdev->dev.of_node,
+ "firmware1", &fw_name)) {
+ dev_err(&pdev->dev,
+ "failed to load firmware filename\n");
+ return 0;
+ }
+ break;
+ case SOC_TYPE_VR9_2:
+ if (of_property_read_string(pdev->dev.of_node,
+ "firmware2", &fw_name)) {
+ dev_err(&pdev->dev,
+ "failed to load firmware filename\n");
+ return 0;
+ }
+ break;
+ }
+ } else if (of_property_read_string(pdev->dev.of_node,
+ "firmware", &fw_name)) {
dev_err(&pdev->dev, "failed to load firmware filename\n");
return 0;
}
--=20
1.7.10.4

[John Crispin]

The voice and dsl drivers need to know which SoC we are running on.

Signed-off-by: =C3=81lvaro Fern=C3=A1ndez Rojas <***@gmail.com>
---
arch/mips/include/asm/mach-lantiq/lantiq.h | 2 ++
arch/mips/lantiq/prom.c | 5 +++++
2 files changed, 7 insertions(+)

diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/inc=
lude/asm/mach-lantiq/lantiq.h
index f196cce..4e5ae65 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -48,6 +48,8 @@ extern struct clk *clk_get_ppe(void);
extern unsigned char ltq_boot_select(void);
/* find out what caused the last cpu reset */
extern int ltq_reset_cause(void);
+/* find out the soc type */
+extern int ltq_soc_type(void);
=20
#define IOPORT_RESOURCE_START 0x10000000
#define IOPORT_RESOURCE_END 0xffffffff
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 7447d32..157f590 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -36,6 +36,11 @@ const char *get_system_type(void)
return soc_info.sys_type;
}
=20
+int ltq_soc_type(void)
+{
+ return soc_info.type;
+}
+
void prom_free_prom_memory(void)
{
}
--=20
1.7.10.4

[John Crispin]

The eiu init failed as the irq_domain was not yet available.

Signed-off-by: John Crispin <***@openwrt.org>
---
arch/mips/lantiq/irq.c | 48 ++++++++++++++++++++++++------------------------
1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 030568a..7bdbd2d 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -378,30 +378,6 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
panic("Failed to remap icu memory");
}

- /* the external interrupts are optional and xway only */
- eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
- if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
- /* find out how many external irq sources we have */
- exin_avail = of_irq_count(eiu_node);
-
- if (exin_avail > MAX_EIU)
- exin_avail = MAX_EIU;
-
- ret = of_irq_to_resource_table(eiu_node,
- ltq_eiu_irq, exin_avail);
- if (ret != exin_avail)
- panic("failed to load external irq resources");
-
- if (request_mem_region(res.start, resource_size(&res),
- res.name) < 0)
- pr_err("Failed to request eiu memory");
-
- ltq_eiu_membase = ioremap_nocache(res.start,
- resource_size(&res));
- if (!ltq_eiu_membase)
- panic("Failed to remap eiu memory");
- }
-
/* turn off all irqs by default */
for (i = 0; i < MAX_IM; i++) {
/* make sure all irqs are turned off by default */
@@ -458,6 +434,30 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
if (MIPS_CPU_TIMER_IRQ != 7)
irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);

+ /* the external interrupts are optional and xway only */
+ eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
+ if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
+ /* find out how many external irq sources we have */
+ exin_avail = of_irq_count(eiu_node);
+
+ if (exin_avail > MAX_EIU)
+ exin_avail = MAX_EIU;
+
+ ret = of_irq_to_resource_table(eiu_node,
+ ltq_eiu_irq, exin_avail);
+ if (ret != exin_avail)
+ panic("failed to load external irq resources");
+
+ if (request_mem_region(res.start, resource_size(&res),
+ res.name) < 0)
+ pr_err("Failed to request eiu memory");
+
+ ltq_eiu_membase = ioremap_nocache(res.start,
+ resource_size(&res));
+ if (!ltq_eiu_membase)
+ panic("Failed to remap eiu memory");
+ }
+
return 0;
}

[John Crispin]

This is a regression caused by:
commit afb46f7996e91aeb36e07bc92cf96e8045bec00e
Author: Rob Herring <***@kernel.org>
Date: Wed Apr 2 19:07:24 2014 -0500
mips: ralink: convert to use unflatten_and_copy_device_tree

Make the of init code reuse the cmdline defined inside the dts.

Signed-off-by: John Crispin <***@openwrt.org>
---
arch/mips/lantiq/prom.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 157f590..a71dc1a 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -77,6 +77,8 @@ void __init plat_mem_setup(void)
* parsed resulting in our memory appearing
*/
__dt_setup_arch(__dtb_start);
+
+ strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
}

void __init device_tree_init(void)

[John Crispin]

The code to detect unfused SoCs was broken due to missing register masking.

Signed-off-by: Thomas Langer <***@lantiq.com>
Signed-off-by: John Crispin <***@openwrt.org>
---
arch/mips/lantiq/falcon/sysctrl.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index 8f1866d..92cf10e 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -147,12 +147,11 @@ static void falcon_gpe_enable(void)
if (status & (1 << (GPPC_OFFSET + 1)))
return;

- if (status_r32(STATUS_CONFIG) == 0)
+ freq = (status_r32(STATUS_CONFIG) &
+ GPEFREQ_MASK) >>
+ GPEFREQ_OFFSET;
+ if (freq == 0)
freq = 1; /* use 625MHz on unfused chip */
- else
- freq = (status_r32(STATUS_CONFIG) &
- GPEFREQ_MASK) >>
- GPEFREQ_OFFSET;

/* apply new frequency */
sysctl_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),

[John Crispin]

Signed-off-by: Thomas Langer <***@lantiq.com>
Signed-off-by: John Crispin <***@openwrt.org>
---
arch/mips/lantiq/falcon/sysctrl.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index 92cf10e..c000b56 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -49,6 +49,7 @@

/* Activation Status Register */
#define ACTS_ASC0_ACT 0x00001000
+#define ACTS_SSC0 0x00002000
#define ACTS_ASC1_ACT 0x00000800
#define ACTS_I2C_ACT 0x00004000
#define ACTS_P0 0x00010000
@@ -259,5 +260,6 @@ void __init ltq_soc_init(void)
clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4);
clkdev_add_sys("1e100b00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT);
clkdev_add_sys("1e100c00.serial", SYSCTL_SYS1, ACTS_ASC0_ACT);
+ clkdev_add_sys("1e100d00.spi", SYSCTL_SYS1, ACTS_SSC0);
clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
}

[John Crispin]

There is a lot of redundant code. Put this into a helper function.

Signed-off-by: Thomas Langer <***@lantiq.com>
Signed-off-by: John Crispin <***@openwrt.org>
---
arch/mips/lantiq/falcon/sysctrl.c | 97 ++++++++++++++++---------------------
1 file changed, 41 insertions(+), 56 deletions(-)

diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index c000b56..dbfe18d 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -63,17 +63,26 @@
#define ACTS_PADCTRL3 0x00200000
#define ACTS_PADCTRL4 0x00400000

-#define sysctl_w32(m, x, y) ltq_w32((x), sysctl_membase[m] + (y))
-#define sysctl_r32(m, x) ltq_r32(sysctl_membase[m] + (x))
+#define sysctl_w32(m, val, reg) ltq_w32((val), sysctl_membase[m] + (reg))
+#define sysctl_r32(m, reg) ltq_r32(sysctl_membase[m] + (reg))
#define sysctl_w32_mask(m, clear, set, reg) \
sysctl_w32(m, (sysctl_r32(m, reg) & ~(clear)) | (set), reg)

-#define status_w32(x, y) ltq_w32((x), status_membase + (y))
-#define status_r32(x) ltq_r32(status_membase + (x))
+#define status_w32(val, reg) sysctl_w32(3, val, reg)
+#define status_r32(reg) sysctl_r32(3, reg)

-static void __iomem *sysctl_membase[3], *status_membase;
+static const char * const sysctrl_compatible[] = {
+ "lantiq,sys1-falcon",
+ "lantiq,syseth-falcon",
+ "lantiq,sysgpe-falcon",
+ "lantiq,status-falcon",
+ "lantiq,ebu-falcon"
+};
+
+static void __iomem *sysctl_membase[ARRAY_SIZE(sysctrl_compatible)];
void __iomem *ltq_sys1_membase, *ltq_ebu_membase;

+
void falcon_trigger_hrst(int level)
{
sysctl_w32(SYSCTL_SYS1, level & 1, SYS1_HRSTOUTC);
@@ -182,62 +191,38 @@ static inline void clkdev_add_sys(const char *dev, unsigned int module,
clkdev_add(&clk->cl);
}

+void __iomem * __init sysctrl_init(const char *compatible)
+{
+ struct device_node *np;
+ struct resource res;
+ void __iomem *base;
+
+ np = of_find_compatible_node(NULL, NULL, compatible);
+ if (!np)
+ panic("Failed to load node '%s'", compatible);
+
+ if (of_address_to_resource(np, 0, &res))
+ panic("Failed to get '%s' resources", compatible);
+
+ if (request_mem_region(res.start, resource_size(&res), res.name) < 0)
+ pr_err("Failed to request '%s' mem-region\n", compatible);
+
+ base = ioremap_nocache(res.start, resource_size(&res));
+ if (!base)
+ panic("Failed to remap '%s' resources", compatible);
+
+ return base;
+}
+
void __init ltq_soc_init(void)
{
- struct device_node *np_status =
- of_find_compatible_node(NULL, NULL, "lantiq,status-falcon");
- struct device_node *np_ebu =
- of_find_compatible_node(NULL, NULL, "lantiq,ebu-falcon");
- struct device_node *np_sys1 =
- of_find_compatible_node(NULL, NULL, "lantiq,sys1-falcon");
- struct device_node *np_syseth =
- of_find_compatible_node(NULL, NULL, "lantiq,syseth-falcon");
- struct device_node *np_sysgpe =
- of_find_compatible_node(NULL, NULL, "lantiq,sysgpe-falcon");
- struct resource res_status, res_ebu, res_sys[3];
int i;

- /* check if all the core register ranges are available */
- if (!np_status || !np_ebu || !np_sys1 || !np_syseth || !np_sysgpe)
- panic("Failed to load core nodes from devicetree");
-
- if (of_address_to_resource(np_status, 0, &res_status) ||
- of_address_to_resource(np_ebu, 0, &res_ebu) ||
- of_address_to_resource(np_sys1, 0, &res_sys[0]) ||
- of_address_to_resource(np_syseth, 0, &res_sys[1]) ||
- of_address_to_resource(np_sysgpe, 0, &res_sys[2]))
- panic("Failed to get core resources");
-
- if ((request_mem_region(res_status.start, resource_size(&res_status),
- res_status.name) < 0) ||
- (request_mem_region(res_ebu.start, resource_size(&res_ebu),
- res_ebu.name) < 0) ||
- (request_mem_region(res_sys[0].start,
- resource_size(&res_sys[0]),
- res_sys[0].name) < 0) ||
- (request_mem_region(res_sys[1].start,
- resource_size(&res_sys[1]),
- res_sys[1].name) < 0) ||
- (request_mem_region(res_sys[2].start,
- resource_size(&res_sys[2]),
- res_sys[2].name) < 0))
- pr_err("Failed to request core reources");
-
- status_membase = ioremap_nocache(res_status.start,
- resource_size(&res_status));
- ltq_ebu_membase = ioremap_nocache(res_ebu.start,
- resource_size(&res_ebu));
-
- if (!status_membase || !ltq_ebu_membase)
- panic("Failed to remap core resources");
-
- for (i = 0; i < 3; i++) {
- sysctl_membase[i] = ioremap_nocache(res_sys[i].start,
- resource_size(&res_sys[i]));
- if (!sysctl_membase[i])
- panic("Failed to remap sysctrl resources");
- }
+ for (i = 0; i < ARRAY_SIZE(sysctrl_compatible); i++)
+ sysctl_membase[i] = sysctrl_init(sysctrl_compatible[i]);
+
ltq_sys1_membase = sysctl_membase[0];
+ ltq_ebu_membase = sysctl_membase[4];

falcon_gpe_enable();