Stefan Hengelein
2014-10-19 18:04:26 UTC
When CONFIG_MIPS_MT_SMP is enabled, the following compilation error
occurs:
arch/mips/pmcs-msp71xx/msp_irq_cic.c:134: error: =E2=80=98irq=E2=80=99 =
undeclared
This code clearly never saw a compiler.
The surrounding code suggests, that 'd->irq' was intended, not
'irq'.
This error was found with vampyr.
Signed-off-by: Stefan Hengelein <***@fau.de>
---
arch/mips/pmcs-msp71xx/msp_irq_cic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/pmcs-msp71xx/msp_irq_cic.c b/arch/mips/pmcs-msp7=
1xx/msp_irq_cic.c
index b8df2f7..1207ec4 100644
--- a/arch/mips/pmcs-msp71xx/msp_irq_cic.c
+++ b/arch/mips/pmcs-msp71xx/msp_irq_cic.c
@@ -131,11 +131,11 @@ static int msp_cic_irq_set_affinity(struct irq_da=
ta *d,
int cpu;
unsigned long flags;
unsigned int mtflags;
- unsigned long imask =3D (1 << (irq - MSP_CIC_INTBASE));
+ unsigned long imask =3D (1 << (d->irq - MSP_CIC_INTBASE));
volatile u32 *cic_mask =3D (volatile u32 *)CIC_VPE0_MSK_REG;
=20
/* timer balancing should be disabled in kernel code */
- BUG_ON(irq =3D=3D MSP_INT_VPE0_TIMER || irq =3D=3D MSP_INT_VPE1_TIMER=
);
+ BUG_ON(d->irq =3D=3D MSP_INT_VPE0_TIMER || d->irq =3D=3D MSP_INT_VPE1=
_TIMER);
=20
LOCK_CORE(flags, mtflags);
/* enable if any of each VPE's TCs require this IRQ */
--=20
1.9.1
occurs:
arch/mips/pmcs-msp71xx/msp_irq_cic.c:134: error: =E2=80=98irq=E2=80=99 =
undeclared
This code clearly never saw a compiler.
The surrounding code suggests, that 'd->irq' was intended, not
'irq'.
This error was found with vampyr.
Signed-off-by: Stefan Hengelein <***@fau.de>
---
arch/mips/pmcs-msp71xx/msp_irq_cic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/pmcs-msp71xx/msp_irq_cic.c b/arch/mips/pmcs-msp7=
1xx/msp_irq_cic.c
index b8df2f7..1207ec4 100644
--- a/arch/mips/pmcs-msp71xx/msp_irq_cic.c
+++ b/arch/mips/pmcs-msp71xx/msp_irq_cic.c
@@ -131,11 +131,11 @@ static int msp_cic_irq_set_affinity(struct irq_da=
ta *d,
int cpu;
unsigned long flags;
unsigned int mtflags;
- unsigned long imask =3D (1 << (irq - MSP_CIC_INTBASE));
+ unsigned long imask =3D (1 << (d->irq - MSP_CIC_INTBASE));
volatile u32 *cic_mask =3D (volatile u32 *)CIC_VPE0_MSK_REG;
=20
/* timer balancing should be disabled in kernel code */
- BUG_ON(irq =3D=3D MSP_INT_VPE0_TIMER || irq =3D=3D MSP_INT_VPE1_TIMER=
);
+ BUG_ON(d->irq =3D=3D MSP_INT_VPE0_TIMER || d->irq =3D=3D MSP_INT_VPE1=
_TIMER);
=20
LOCK_CORE(flags, mtflags);
/* enable if any of each VPE's TCs require this IRQ */
--=20
1.9.1