John Crispin
2014-10-13 11:16:18 UTC
While updating the mt7621 code to make use of the mips-cm i had to apply the
following patch to get the unit booting. With this patch applied the SoC boots
fine with and all 4 cores work.
The MT7621 has a broken iocu so i guess this might be related ? could someone that
actually knows what those registers do enlighten me please :)
Signed-off-by: John Crispin <***@openwrt.org>
---
arch/mips/kernel/mips-cm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
index f76f7a0..38835c2 100644
--- a/arch/mips/kernel/mips-cm.c
+++ b/arch/mips/kernel/mips-cm.c
@@ -105,6 +105,7 @@ int mips_cm_probe(void)
write_gcr_base(base_reg);
/* disable CM regions */
+ /*
write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
@@ -113,7 +114,7 @@ int mips_cm_probe(void)
write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
-
+ */
/* probe for an L2-only sync region */
mips_cm_probe_l2sync();
following patch to get the unit booting. With this patch applied the SoC boots
fine with and all 4 cores work.
The MT7621 has a broken iocu so i guess this might be related ? could someone that
actually knows what those registers do enlighten me please :)
Signed-off-by: John Crispin <***@openwrt.org>
---
arch/mips/kernel/mips-cm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
index f76f7a0..38835c2 100644
--- a/arch/mips/kernel/mips-cm.c
+++ b/arch/mips/kernel/mips-cm.c
@@ -105,6 +105,7 @@ int mips_cm_probe(void)
write_gcr_base(base_reg);
/* disable CM regions */
+ /*
write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
@@ -113,7 +114,7 @@ int mips_cm_probe(void)
write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
-
+ */
/* probe for an L2-only sync region */
mips_cm_probe_l2sync();
--
1.7.10.4
1.7.10.4